Indian Institute of Information Technology, Nagpur
Indian Institute of Information Technology, Nagpur

भारतीय सूचना प्रौद्योगिकी संस्था, नागपूर

Indian Institute of Information Technology, Nagpur

Institute of National Importance By The Act of Parliament | The Indian Institute of Information Technology (PPP) Act, 2017
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Research Domain High Performance Computing

 

Operating System level Solutions for Energy Efficiency of Heterogeneous Multi-cores in Dark Silicon Era

Dark silicon era refers to the era of the system-on-chip multiprocessor technology  where only a fraction of on-chip resources (like processing cores, cache blocks, hardware accelerators etc) can be put in power-on mode due to limited power budget and safe thermal limits, while the other on-chip resources are required to be kept in power-off mode or "dark".

The continuous feature size scaling of the transistors (as stated by Moore's law) resulted in abundance of transistors on the same chip area. But all the transistors cannot be powered-on simultaneously due to power and thermal constraints. 

The scaling of feature size till some threshold value scales the voltage and current, increases the frequency and keeps the power per unit area constant (Dennard Scaling rule), but below this threshold value, the  voltage cannot be further reduced since it increases the  leakage current exponentially which further results in significant increase in power consumption and temperature. Below 65nm technology, Dennard scaling also fails.

The only solution to take advantage of the decreasing size of transistors (or increase in number of transistors per die) is to keep the fraction of on-chip resources in power-off mode and to use only fraction of resources at run time. In order to make good choices of these resources, heterogeneous multi-core is one of the effective processor architectures that leverage this abundance of transistors to increase performance, energy efficiency and reliability under power and thermal constraints.

For the heterogeneous multi-core processor architectures where the cores with different functional characteristics (CPU, GPU, DSP etc) and the cores with different performance-energy characteristics (simple verses complex micro-architecture) co-exist on the same die, the application can be executed by exploiting only the cores that best fit a particular application leading to faster and energy efficient computing. It leaves rest of the cores in power-off mode or "dark". Various other techniques such as dynamic voltage and frequency scaling, dynamic power management etc also exist to optimize the energy consumption of the processor cores.

Another motivation behind focusing on energy efficient solutions for multi-core processors is that the majority of the today's embedded systems (which are made up of multi-core processors) and are supposed to give high performance, longer battery life and perform highly critical applications (in case of real time embedded systems) are battery operated. Therefore, there is a need to optimize energy consumption of such devices to prolong their duration on a single charge.

Application Area:

  • Embedded Systems
  • Power hungry devices and processors used in IoT based Systems
  • Bioinformatics and Computational Biology
  • Cyrptography
  • Deep Learning
  • Larger Interger Multiplication


 

Faculty Associated with the research group:

 

 

 

 

Dr. Jitendra V. Tembhurne

Dr. Tausif Diwan

Dr. Mayuri Digalwar

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